2.1.2.3. Semiconductor Yield Modeling Using Generalized Linear Models by Dana Cheree Krueger A Dissertation Presented in Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy Approved March 2011 by the Graduate Supervisory Committee: Douglas C. Montgomery, Chair John Fowler Rong Pan Michele Pfund ARIZONA STATE UNIVERSITY May 2011 . 3D-Micromac AG Recommended for … and solutions to warpage, because (as will be discussed) Stoney’s formula (relating intrinsic stress and curvature) does not apply for structures warped with compound curvature, and standard wafer warpage measurements are not designed to measure compound curvature. the number of dies per wafer, and give an explanation of your formula. threshold voltages or transistor gains) on the yield. You can simplify the formula for rolled throughput yield as. The gross yield limits for clusters of defects can be calculated by overlaying clustered defects wafer maps with probe wafer maps. TSMC is actually open and transparent with their progress and metrics. The required parameters for calculating the gross die per wafer are the die size, the edge exclusion and the wafer size. N G =Gross die per wafer. L8 3 C. J. Spanos The fraction non-conforming The most inexpensive statistic is the yield of the production line. Effective Area. Wafer size transitions historically account for 4 percent of the 25-30 percent productivity gain. Semiconductors; Taiwan; Japan; China; CMOS Process Animation; Contact. N G =Gross die per wafer . a) Find the yield for both wafers. Companies make wafer size transitions because of the overall cost benefits resulting from the larger number of dice per wafer, thereby using the same number of process steps to produce more dice. Second, the number of devices per wafer is increased. Then, the percent yield would be: Percentage yield of NaCl = 8.50 grams ÷ 9.93 grams × 100%. i.e Very Good. The gross yield limits for clusters of defects can be calculated by overlaying clustered defects wafer maps with probe wafer maps. In electronics, a wafer (also called a slice or substrate) is a thin slice of semiconductor, such as a crystalline silicon (c-Si), used for the fabrication of integrated circuits and, in photovoltaics, to manufacture solar cells.The wafer serves as the substrate for microelectronic devices built in and upon the wafer. Various models  have been constructed for estimating the device yield of a wafer - usually based on the die size, process linewidth, and particle accumulation. It is defect density per cm2 that is the most important factor. As part of this problem, you will want to derive a formula for the die area (note that this will be an approximation). (all products, modest yield) • Value/Mass of processed wafer \$275,000/Kg . The wafer device yield plays a very important role in cost-effectiveness for Integrated Circuit (IC) manufacturers. The die size is the stepping distance on the wafer and not the size of the die after saw. Even if the first time yields of the individual process steps are high, if the overall process becomes more and more complex, the system rolled throughput yield will continue to erode. Let’s assume that you obtained an actual yield of 8.50 grams. Silicon wafers are ubiquitous in pretty much every electronic device around us. A formula is derived to calculate the amount of improvement expected after redundancy. Notes Use this form to calculate the gross die per wafer and net yield at the wafer level. N D =Total number of die affected by clusters . • Infant Mortality is measured by life-test, and controlled by burn in. • Defect densities, calculated for major process flows in each fab by using reported die yields and die sizes in the Murphy model of defect density. Solving both equations for Z, the value can be determined simply by: Z = (B – A)/2. Percentage yield … The formula for calculating the percent yield is: Percentage yield = mass of actual yield ÷ mass of theoretical yield × 100%. It is a popular material used to manufacture semiconductors. Use 1 gross die, 2 for net die and 3 for wafer yield. Die-Per-Wafer Estimator; Gallery. where the capital Greek letter pi (Π) tells you to multiply all the first time yields of the system together. This is because there are many variables that affect yield, and this method uses wafer averages and determines the average effect of electrical parameters (e.g. Fabrication Yield - Georgia Tech - HPCA: Part 1 Udacity. For single chip yield, Murphy’s formula can simply be applied twice: is the average function reflecting the distribution of defect densities among the wafers considered. estimated weight vector to the actual yield, and classify wafers through clustering analysis in order to detect abnormal wafers and plan future production. CS 514 Homework 1 A NEESH K ULKARNI CWID 10427145 Case Study 1 1.1 a) Die Yield is given by the formula, Die Yield = Wafer Yield x 1/ (1 + (Defects per unit area x Die Area)) ^N Let us assume a wafer yield of 100% Die Yield of phoenix chip = (8*10^7) / (7*10^-7 * 12*10^9) X 1/ ( 1+ (200*10^-2 *0.04)^14 = approx. Another yield consideration is interwafer (wafer to wafer) defect density variation. Cost per die = (Cost per wafer / (dies per wafer × yield)) Dies per wafer ≈ Wafer area / Die Area Die Area ≈ Wafer area / Dies per wafer Yield = (1 + (Defects per area × Die area/2))^(-2) or Yield = 1/((1 + (Defects per area × Die area/2))^2) What are response time and throughput and how are they affected by 1) replacing a processor with a faster one or by 2) adding more processors. Service-based businesses calculate the formula slightly differently: by multiplying the number of customers by the average service price. A block redundancy scheme is used here, where the entire defective memory subarray is replaced by a redundant element. –Life test is an extended burn in designed to acquire detailed reliability data. N AV =Average number of die affected per cluster. 3. Die Yield = Wafer yield * 1 + Defects_per_unit_area * Die_Area Integrated Circuits Costs Die Cost goes roughly with die area 4 { } RHK.S96 9 Real World Examples Chip Metal Line Wafer Defect Area Dies/ Yield Die Cost layers width cost /cm 2 mm 2 wafer 386DX 2 0.90 \$900 1.0 43 360 71% \$4 486DX2 3 0.80 \$1200 1.0 81 181 54% \$12 PowerPC 601 4 0.80 \$1700 1.3 121 115 28% \$53 HP PA 7100 3 0.80 \$1300 … Quality and material yield are two fundamental drivers of wafer TCO, as shown in the mathematical formula. ( Your yield percentage change due to design and die size ) 2. per die Cost per wafer Dies per wafer yield× = -----waferper -----Wafer area Die area ≈ - 1 ()1 Defects+ ()per area Die× area 2 ⁄ 2-----= IMD 1.8-2 In More Depth 1.61  <§§1.4, 1.5> What is the approximate cost of a die in the wafer shown in Figure 1.15 on page 31? • Average line yield, the percentage of wafers started that are completed properly, normalized to twenty mask layers. Even if the yield decreases with the implementation of smaller features, the total number of functioning devices per wafer may still be a greater number than without the shrink, with larger features . The reported defect densities account for all yield losses, including both spot defects and parametric problems. The formula for the yield limit is: ##EQU6## where: ##EQU7## P k i = N C =Number of clustered defects . Ybatch is the fraction of integrated circuits which on each wafer which are fully functional at the end of the line. Production of Silicon Wafers • Silicon starts as beach sand quartzite . One important aspect that directly hit the quality is the silicon wafer yield analysis and wafer yield analysis can help the engineers to identify the causes of failures at a very early stage. The formula for the yield limit is: Y i = 1-(N C * N AV N * N G) * P k (6) where: P k i = N CD N D. P k i = N C =Number of clustered defects. It is no use discussing yield % without putting the die size. Silicon is the principle platform for semiconductor devices. incremental yield improvements. ii ABSTRACT Yield is a key process … Steep yield ramp means quicker path to high batch yield and hence volume production. N AV =Average number of die affected per cluster . • Burn in is a stress preceding final test which activates latent reliability defects (LRDs) so that they may be screened out at final test (Class). In a nutshell, "yields" in the slide mentioned above refer to what percentage of the chips on a given semiconductor wafer actually work. The groundwork for applying wafer-level spatial variation decomposition was laid in , wherein the authors used a set of predeﬁned basis functions. Yield is related to the ratio of defective vs. non-defective, conforming vs. non-conforming or functional vs. non-functional. Index words: Poisson’s formula, yield, defect density, repair rate Abstract This paper describes a model developed to calculate the number of redundant good die per wafer. Z = Distance between wafer median surface and the point halfway between the upper and lower probe (D/2) To determine the value of Z at any location on the wafer, there are two equations: Z = D/2 – A – T/2 and Z= -D/2 + B + T/2. Wafer manufacturers look for a minimum of 95% quality yield with increasingly tight wafer specifications. • Yield is measured at Sort – initial wafer-level testing. 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